1. Field of the Invention
The present invention relates to termination of transmission lines and, in particular, the present invention relates to receiver termination of devices-under-test (DUTS) in automatic testing equipment (ATE).
2. Statement of the Problem
The termination of transmission lines represents an area of signal analysis that has been well studied. See, for example, Javid and Brenner, Analysis Transmission and Filtering of Signals, "Transmission Lines 1-Transients", Pages 334-347, 1981 (Robert E. Krieger Publishing Co., Inc., Malabar, FL).
The goal of ATE systems is to provide a test interface to a large number of different types of DUTs. The ATE system applies a stimulus to the DUT and then looks for an appropriate signal response. For digital DUTs, the ATE system drivers drive the correct logic levels for a valid "1" or "0" to the inputs of the DUT and then the digital receivers in the ATE system look for a valid "1" or "0" at the outputs.
In FIG. 1a, a typical device-under-test (DUT) interconnected through a fixture and a printed circuit (PC) board 20 with an automatic test equipment (ATE) system 30 containing a receiver 40 and a driver 60. Receiver 40 in an ATE system (generally indicated at 30) probes the DUT 10 in order to determine the function of the circuit without interfering with the operation of the circuit. This normally implies keeping the input 50 to the receiver at a high impedance. However, the connection of the receiver 40 to the DUT 10 adds some parasitic capacitance C.sub.P to ground thereby partially affecting the operation of the DUT.
An optional three state driver 60, shown in dotted lines, may be selectively interconnected by means of a switch 70 to the input 50 to drive a signal into the DUT.
The ATE system 30 contains a number of receivers 40 and drivers 60 and will be discussed more fully with respect to FIG. 2.
In FIG. 1a, when the receiver 40 input impedance is high compared to the impedance Z.sub.O of the fixture in PC board 20 and the source output resistance R.sub.S is low (compared to Z.sub.O) then the waveform from the DUT at the receiver input 50 will overshoot. This results in a classic ringing problem. If R.sub.S is small, a larger voltage (hence, more current) will be delivered down the transmission line by the DUT. In other words, the waveform at the receiver 40 overshoots the source voltage V.sub.S from the DUT and then undershoots below V.sub.S. The amount of current initially sent down the line is determined by the instantaneous impedance seen at the R.sub.2 -Z.sub.O interface. As the waveform travels down the transmission line it then encounters the Z.sub.O - input 50 of receiver 40 interface. The receiver 40 typically is of much higher impedance than Z.sub.O thereby causing the voltage waveform to overshoot. (Note: The initial voltage sent down the line is ##EQU1## when R.sub.S is small, a good approximation for many of these high speed DUTs.) Eventually, the ringing damps down to a steady state value of V.sub.S. In an ATE system, one of the problems is to design the receiver 40 such that it is capable of interfacing with many different DUTs having varying output impedances in a fashion to minimize the ringing problem. Hence, a low cost, easy to implement design for receiver 40 is needed.
The problem of ringing is further enhanced when short wire length PC fixtures 20 are required because of the high speed of the digital circuits found in the DUTs (i.e., this assumes a lossy transmission line). Hence, a need also exists in the design of a receiver 40 that provides minimum impact on the DUT 10 (that is, having no DC loading and no degradation of AC performance) but which is inexpensive and easy to implement.
There are several ways to conventionally terminate a receiver 40 for ATE equipment and these are illustrated in FIGS. 1b through 1d. In FIG. 1b, a resistive load R.sub.L is connected from input 50 of the receiver 40 to ground. The resistor R.sub.L equals Z.sub.O. This particular termination works well provided the DUT can output a sufficient amount of current (I=V.sub.S +(R.sub.L +R.sub.S +R.sub.DC)) and provided R.sub.S is small compared to R.sub.L +Z.sub.O. R.sub.DC is the lumped resistance of the transmission line. Furthermore, there is no mismatch or reflection at the receiver input 50 since R.sub.L =Z.sub.O. One disadvantage of the prior approach of FIG. 1b is that the DUT 10 must be able to supply the aforesaid value of current to the transmission line 20 when driving high. Many DUTs 10 cannot supply that amount of current.
In FIG. 1c, a second prior art solution for terminating a receiver 40 in an ATE system 30 is shown. A resistor R.sub.L which is equal to Z.sub.O is terminated on the variable drive 60. A second resistance R.sub.A is added at the output 80 of the DUT 10. The addition of resistor R.sub.A further isolates the DUT 10 from the ATE system 30. But the addition of resistor R.sub.A also means that the parasitic capacitance C.sub.PDUT becomes more important. If a correct value of R.sub.A can be found, the DUT 10 can be adequately isolated from the ATE 30. The problems with the prior art approach shown in FIG. 1c are substantial. For some DUTs 10 there is no good value for R.sub.A. The presence of parasitic capacitance C.sub.PDUT can potentially limit the speed of the ATE in conducting the test. Furthermore, driver 60 now must drive through both R.sub.L and R.sub.A which may be a problem when overdriving (a lot of current may be required). Overdriving occurs when the driver 60 drives a node to a known state regardless of where an enabled upstream device may wish to drive the node. Finally, the implementation of FIG. 1c requires R.sub.A to be physically close to the DUT 10 which involves fixturing problems.
In FIG. 1d, the most common technique which is frequently used in industry is set forth. Here, a resistor R.sub.L is connected in a series connection to a capacitor C.sub.L which connects the input 50 of receiver 40 to ground. Capacitor C.sub.L isolates the resistor R.sub.L from ground. Hence, the resistor R.sub.L does not DC load the DUT 10 but the capacitor C.sub.L will add to the receiver input capacitance which can limit test speed. The clear advantage of the approach of FIG. 1d is that the resistor R.sub.L is only "present" in the circuit when a signal transition from the DUT 10 occurs at the input 50. Termination is only present when the signal at the input 50 is changing state. Hence, no DC loading. One disadvantage with the prior art approach of FIG. 1d requires that Z.sub.O must be well controlled as inductance of the line 20 can form a tank circuit with R.sub.L and C.sub.L which would cause oscillations. Furthermore, C.sub.L will add to the receiver 40 additional parasitic capacitance and increase the effective input capacitance presented to the DUT thereby limiting the speed and performance of the DUT 10.
A need therefore exists for a receiver which can be selectively programmed to a specific DUT 10 which will provide a necessary termination at the input 50 to absorb energy from ringing. The design of this circuit must not interfere with the acquisition of a valid high or low signal from a wide variety of different types of DUTs 10.
FIG. 2 illustrates a typical prior ATE system capable of interfacing with a number of DUTs 10. In FIG. 2, the ATE system 30 includes a set of analog multiplexors (MUX.sub.O - MUX.sub.I ) (e.g., relays) wherein each multiplexor is interconnected over a fixture and PC board 20 to a plurality of DUTs 10 (DUT.sub.A - DUT.sub.N). Other prior art approaches use different techniques to connect the receivers to an individual DUT (such as changing fixtures, etc.). Hence, each receiver termination 50 can be selectively connected by the multiplexor to a discrete DUT 10 in a set of DUTs 10. A measurement can then be taken by the receiver 40 of the signal output of the connected DUT. The receiver termination 210 in FIG. 2 may constitute any one of the above prior art approaches fully discussed in FIG. 1.
The DUTs 10 as shown in FIG. 2 may be of a number of different logic families. These different logic families will have different valid logic thresholds. For example, transistor-transistor logic (TTL) has a signal threshold of 2.0 volts and complementary metal oxide semiconductor (CMOS) has a signal threshold of 4.0 volts, both for a valid digital "1." Furthermore, the output impedance of each logic family is also different. Hence, a need exists for each receiver to have active termination thresholds so as to adjust to the signal characteristics of the DUT being tested.
Since many different logic families may be represented in the DUTs 10, ATEs are presently available wherein each receiver 40 has programmable thresholds on a per receiver basis (e.g., receiver high, receiver low, drive high, drive low). This capability is called "per-pin programmable logic threshold" in the industry. Finally, a need exists to provide distributed programmable clamps on a per-pin basis so as to provide an active termination for the receivers 40.
2. Results of a Patentability Search
A patentability search was directed in the field of the invention to the solution of the above problem. The results of the patentability search generated the following patents:
______________________________________ Muench, Jr. 3,600,634 8-17-71 Andrews, Jr. 3,660,675 5-2-72 Dasgupta et al. 3,832,575 8-27-74 Davis 4,450,370 5-22-84 Slaughter 4,943,739 7-24-90 ______________________________________
U.S. Pat. No. 3,660,675 sets forth a design for terminating a low output impedance source by adding a series termination when the device is sinking, in a diode (no series termination) when the device is sourcing.
U.S. Pat. No. 4,450,370 sets forth an active termination for a transmission line involving a tri-state buffer enabled by a strobe signal. The output of the tri-state buffer is tied through a resistive element which is used to help match the line impedance of the transmission line.
U.S. Pat. No. 3,832,575 sets forth a data bus transmission line termination circuit which is programmable to either a low impedance state for connection to the terminal end of the data bus or to a high impedance state for connection to an intermediate portion of the data bus.
U.S. Pat. No. 3,600,634 issued to Muench, Jr. sets forth a protective control circuit against transient voltages utilizing a pair of solid state gate controlled AC switches. This patent deals with an over voltage circuit which shunts around a load for protection if an over voltage occurs.
U.S. Pat. No. 4,943,739 sets forth a non-reflecting transmission line termination which contains a reflection attenuator connected between the signal line and the ground line or signal line and the power line. The attenuator clamps the voltage of digital signals between ground potential and the supply line voltage. This invention is the most pertinent of the patents uncovered in the search to the solution of the above problem. However, this invention is not applicable to the environment of ATE systems. The signal swing of '739 must be close to V.sub.CC or to ground and, therefore, is not appropriate for use in an ATE. The '739 patent does not deal with the situation involving different types of DUTS--where, for example, the V.sub.CC is not always the same. Furthermore, the '739 approach requires a third line for V.sub.CC, does not provide for high currents, and does not handle the situation where V.sub.CC is less than ground.
3. Solution to the Problem
The present invention provides a solution to the needs set forth in FIGS. 1 and 2 by providing an active distributed programmable line termination for the receiver 210 which is fully programmable on a per-pin basis in an ATE system. The present invention provides a receiver termination which extracts energy from the output DUT signal only when the signal has passed a defined threshold level. Two embodiments of the present invention are set forth. In the first embodiment, the termination voltage is tied to the per-pin programmable (distributed) receiver threshold while the second embodiment allows the termination voltages to be programmed independently on a per-pin basis. Both embodiments provide per-pin programmability of the terminated voltages. Furthermore, the present invention eliminates AC loading caused when the edges of the DUT signal are going through a transition and provide only small DC loading which is present only when the signal from the DUT has exceeded the termination voltage value.